Announcements & Events

The technological advancements require high speed and low-power integrated circuits to meet the processing demands. The adders are a vital part of any arithmetic and logic unit and hence the processor. Different adder circuits are being devised by various researchers and scientists that requires a smaller to achieve lower delay and reduced power dissipation. A minimal number of transistors has been used to develop various adder circuits for area efficiency. However, designs utilizing eight or ten transistors often fail to produce full swing outputs across all input combinations, leading to inconsistent output levels depending on the input data. Moreover, these configurations typically suffer from limited driving strength. Other designs also encounter similar challenges, including incomplete output swings and higher power consumption. As a result, such adders are generally unsuitable for integrated circuit (IC) design due to their voltage swing limitations. This research addresses these challenges by presenting a highly efficient, fast, and energy-aware full-adder solution suitable for modern low-power and high-performance arithmetic circuits.

We cordially invite all faculty members and students to attend this important event. The defense will take place on Monday, April. 20, 2026, at 02:00 PM. in room B15-3-2-012 at the College of Engineering, University City of Fara’a. Your presence and participation will not only support Mohammed but also foster engaging academic discussion.

We look forward to seeing you there!