Workshop: Designing with VHDL
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Day: 02-04/10/2018, from 16:00 to 18:00
College of Engineering, Building of Electrical Engineering Lab.
Restricted to the Students of Electrical Engineering Department level 8, 9 and 10, limited to 15 seats.
To register please enter the following link: https://goo.gl/Vxn71g
Presented by
Dr. Hassen Loukil